1. Field of the Invention
The invention relates to a method for fabricating a semiconductor integrated circuit, and more specifically, to a method for fabricating an electrostatic discharge device.
2. Description of Related Art
The dimensions of a transistor has largely reduced due to the development of semiconductor technology. More transistors can therefore be assembled within a single chip of limited area to improving the function. However, the reduction of transistor dimensions brings new problems which must be overcome by novel techniques. For example, for a transistor having a channel length of shorter than 1.2 m, carriers with high energy will exist near the drain junction where strong local field is generated. It is probably that these carriers, known as "hot carriers," are driven into the gate oxide layer by a lateral electric field when the gate electrode is biased. As the hot carriers gradually enter and accumulate inside the gate oxide layer, the transconductance of the transistor reduces and the threshold voltage increases, thereby affecting the performance of the transistor.
A lightly-doped drain (LDD) transistor structure has been provided for overcoming the aforementioned hot-carrier effect. Referring to FIG. 1, a LDD transistor is fabricated in a semiconductor substrate 1. The transistor includes a gate oxide layer 10, a gate electrode 11, a sidewall spacer 13, lightly-doped drain/source regions 12 and heavily-doped drain/source regions 14. The gate electrode 11 lies over the gate oxide layer 10, and is isolated from the drain/source regions 12 and 14 by the gate oxide layer 10 and spacer 13. The gate electrode 11, when biased, induces a channel under the gate oxide layer 10 in the substrate 1, thereby electrically connecting the two drain/source regions 12.
The lightly-doped drain/source regions 12 have a same conductivity type (N-type or P-type) as the heavily-doped drain/source regions 14. They are different in their dopant concentrations. The lightly-doped drain/source regions can therefore reduce strength of the local field to prevent the hot-carrier effect. However, as an electrostatic discharge device, a large amount of discharging current crowding in the lightly-doped drain/source regions seriously affects the discharging capability of the transistor. That is, the conventional LDD transistor cannot be a good electrostatic discharge device.
Accordingly, the structure of an LDD transistor must be modified if provided as an electrostatic discharge device. The method for fabricating a conventional electrostatic discharge device will be described in accompaniment with the drawings of FIG. 2A through FIG. 2D. Referring to FIG. 2A, a gate dielectric layer 211 and a gate electrode 212 are successively formed over the substrate of an ESD region 210, whereas a gate dielectric layer 221 and a gate electrode 212 are formed over the substrate of an internal circuit region 220. An ion implantation step is then carried out, using the gate electrodes 212 and 222 as masks, to form lightly-doped source/drain regions 213 and 223 in the substrate 2 of the ESD region 210 and internal circuit region 220, respectively.
Further referring to FIG. 2B, sidewall spacers 214 and 224 are formed on sidewalls of the gate electrode 212 and gate electrode 222, respectively. These sidewall spacers 214 and 224 and the gate electrodes 212 and 222 are then utilized as masks of a second ion implantation step. Referring to FIG. 2C, the second ion implantation step forms heavily-doped source/drain regions 215 and 225 in substrate 2 of the ESD region 210 and internal circuit region 220, respectively.
Referring to FIG. 2D, the internal circuit region 220 is then covered by a photoresist layer 226. A third ion implantation step is carried out, using the gate electrode 212 as a mask, to form a diffusion region 216 in the substrate 2 of the exposed ESD region 210. The diffusion region 216 must cover both the lightly-doped region 213 and the heavily-doped region 215. Since ions must be implanted through the sidewall spacer 214 to cover the lightly-doped region 213 in the substrate 2, a more expensive high implantation energy is required. The high implantation energy also increases the probability of contamination. Moreover, the high-energy implantation may damage the gate electrode, thus causing leakage current.
Another conventional method for fabricating an electrostatic discharge device, as disclosed in U.S. Pat. Nos. 5,529,941 and 5,416,036, will be described in accompaniment with FIG. 3A through FIG. 3D. Referring to FIG. 3A, a gate dielectric layer 311 and a gate electrode 312 are successively formed over the substrate of an ESD region 310, whereas a gate dielectric layer 321 and a gate electrode 322 are formed over the substrate of an internal circuit region 320. An ion implantation step is then carried out, using the gate electrodes 312 and 322 as masks, to form lightly-doped source/drain regions 313 and 323 in the substrate 3 of the ESD region 310 and internal circuit region 320, respectively.
Further referring to FIG. 3B, sidewall spacers 314 and 324 are formed on sidewalls of the gate electrode 312 and gate electrode 322, respectively. Referring to FIG. 3C, a photoresist layer 325 is formed over the internal circuit region 320. The exposed sidewall spacer 314 in the ESD region is then removed by etching. After removing the photoresist layer 325, referring to FIG. 3D, an ion implantation step is carried out to form heavily-doped regions 316 and 326 in the substrate 3 of the ESD region 310 and internal circuit region 320, respectively, by using the gate electrodes 312 and 322 and the sidewall spacer 324.
This method fabricates a non-LDD device in the ESD region. The electrostatic discharge capacity can therefore be improved. However, the hot-carrier effect and short-channel effect will still occur therein. Moreover, the additional etching step for removing the sidewall spacer 314 may affect the conformity of the gate dielectric layer.